1. Field of the Invention
The present invention relates to a structure of an integrated circuit (IC) device, and more particularly, to a semiconductor device.
2. Description of the Related Art
Once the gate length of the silicon metal-oxide semiconductor (MOS) transistor device is reduced to a deep submicron range, because the carrier passing time decreases along with the decrease of the channel length, a device with better performance is obtained. However, many problems still need to be solved in the aspect of fabricating technique thereof. For example, when the device is becoming smaller, the size of the source/drain area reduces accordingly, which increases the contact resistance of the source/drain terminal, thus the device fails to maintain the original high current driving capability.
In order to resolve the problem mentioned above, a silicon-germanium (SixGey) technique has been developed for fabricating an MOS transistor with raised source/drain. Since the silicon-germanium can be selectively grown in the source/drain area as well as selectively etched compared to silicon and silicon oxide, silicon-germanium is a more suitable material for fabricating semiconductor devices compared to silicon. Moreover, since silicon-germanium has a lower energy width than that of silicon, a lower schottky barrier height is existed on the p-type junction, which reduces the contact resistance.
However, the MOS transistor with raised source/drain fabricated by the silicon-germanium technique is likely to cause problems such as film damages during the subsequent fabricating process, for example, in the subsequent cleaning process. Consequently, the reliability of the fabricating process is affected.